一、公司介紹
Cadence(Nasdaq: CDNS)是全球電子設(shè)計(jì)自動(dòng)化(EDA)企業(yè)，從事軟件與硬件設(shè)計(jì)工具、芯片知識(shí)產(chǎn)權(quán)與設(shè)計(jì)服務(wù)。Cadence公司成立于1988年，總部位于加州圣荷塞，其設(shè)計(jì)中心、研發(fā)中心和銷(xiāo)售部門(mén)分布于世界各地。公司網(wǎng)站www.cadence.com.cn
1992年Cadence 公司進(jìn)入中國(guó)大陸市場(chǎng)，迄今已擁有大量的集成電路 (IC) 及系統(tǒng)設(shè)計(jì)客戶(hù)群體。在過(guò)去的二十年里，Cadence公司在中國(guó)不斷發(fā)展壯大，建立了北京、上海、深圳分公司以及北京研發(fā)中心、上海研發(fā)中心，并于2008年將亞太總部設(shè)立在上海，Cadence中國(guó)現(xiàn)有員工600余人。
北京研發(fā)中心(現(xiàn)位于北京市東城區(qū)北三環(huán)東路36號(hào)，北京環(huán)球貿(mào)易中心)和上海研發(fā)中心(現(xiàn)位于上海市浦東嘉里中心)主要承擔(dān)美國(guó)總部EDA軟件研發(fā)任務(wù)，力爭(zhēng)提供給用戶(hù)更加完美的設(shè)計(jì)工具和全流程服務(wù)。Cadence在中國(guó)擁有強(qiáng)大的技術(shù)支持團(tuán)隊(duì)，提供從系統(tǒng)軟硬件仿真驗(yàn)證、數(shù)字前端和后端及低功耗設(shè)計(jì)、數(shù)?；旌蟁F前端仿真與DFM以及后端物理驗(yàn)證、SiP封裝以及PCB設(shè)計(jì)等技術(shù)支持。我們的銷(xiāo)售方案中還包括提供數(shù)字及模擬IP、專(zhuān)業(yè)設(shè)計(jì)服務(wù)，VCAD團(tuán)隊(duì)為用戶(hù)提供高質(zhì)量、有效的設(shè)計(jì)和外包服務(wù)。
欲了解職位詳情請(qǐng)查詢(xún)“就業(yè)機(jī)會(huì)”或關(guān)注Cadence公眾微信平臺(tái)：Cadence中國(guó)招聘
二、招聘崗位
計(jì)算機(jī)，軟件工程，微電子，電子信息工程及相關(guān)專(zhuān)業(yè)
空缺職位
若干。軟件研發(fā)工程師、產(chǎn)品工程師和實(shí)習(xí)生職位空缺在北京和上海。
R&D
1. Senior/Software Engineer--Simulator front-end (Location: BJ)
Position Description:
1.Research and design simulator front end
Position Requirements:
1.Strong C++ programming and familiarity with development under Linux/Unix environment.
2.Proficiency with linux/unix tools.
3.Skills in one or more of script such as Python, Perl.
4.Familiar with build and version-control systems.
5.Good English communication skill both verbally and writing.
6.Good problem solving skill and team work spirit.
2. Senior Software Engineer--Virtuoso Design Environment (Location: BJ)
Position Description:
Custom digital and analog circuit designers must generate and interpret large amounts of complex simulation data. Virtuoso ADE accelerates design by enabling setup reuse, parallelizing and distributing compute-intensive simulation, and through extensive post-processing and visualization capabilities.
As an ADE programmer, you will:
1.Work closely with simulation and visualization teams in order to streamline tool flow and deliver new capabilities.
2.Implement internal algorithms, provide APIs for other tools to integrate, and provide GUI support for the end user.
3.Carefully consider data structures to handle large data sets.
4.Demonstrate strong OO knowledge using C++.
5.Write tests to validate your implementation.
Position Requirements:
1.Skilled in C++ programming, familiar with development under Linux/Unix environment;
2.Familiarity with GUI development, especially using the Qt toolkit is a plus
3.Familiarity with XML and/or SQL is a plus
4.Be familiar with Analog-signal design is a plus;
5.Good English communication skill both verbally and writing;
6.Good problem solving skill and team work spirit;
3. Senior/Software Engineer--Characterization (Location: BJ)
Position Description:
1.The positions are for a developer who will be responsible for designing, implementing, and maintaining library characterization and validation software for use with standard cells, memory and macro blocks, and IO cells
Position Requirements:
1.The candidates should have two or more years of experiences in developing EDA software.
2.Must be proficient in C, C++, TCL, and development in Linux/Unix.
3.Knowledge on semiconductor device is strong plus.
4.Experience with SPICE or SPICE-like circuit simulation is important.
5.Knowledge of Verilog and VHDL is also highly desirable.
6.Have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows.
7.Minimum Education Required / Minimum Experience Required : MS, EE, CS, Math or Physics 2
8.Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math or Physics 3-5
4. Senior Software Engineer--RF Simulator (Location: BJ)
Position Description:
1.The position is responsible for designing, implementing and maintaining Cadence Virtuoso platform for RF simulator. The engineer will be responsible for leading multiple development efforts through the development process, and working with a cross-functional team to ensure the software is tested, integrated and documented.
Position Requirements:
1. Skilled in C++ programming, familiar with development under Linux/Unix environment;
2.Exposure to the Cadence Virtuoso environment
3.Familiarity with Analog, RF or microwave design is a strong plus;
4.Good English communication skill both verbally and writing;
5.Good problem solving skill and team work spirit;
6. Education Requirement: Master in EE, CS, or related.
7.Experience with RF simulation methods, such as Harmonic Balance, Envelope and Shooting Newton
8.Understanding of distributed network theory
9.Background or coursework in RF/microwave circuits
5. Senior/Software Engineer--Power Route (Location: SH)
Position Description:
1. This position is for a R&D engineer to assist in development of special routing(power planning / power routing ...) solution of digital IC design in Encounter.
2. The candidate will be responsible for designing, developing, troubleshooting and debugging software programs of routing flow and related algorithms.
Position Requirements
1. The candidates should have strong software programming skill with C/C++ on Linux/Unix platform.
2. Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills
3. EDA software development experience or IC design knowledge, especially in backend
4. Know basic routing algorithms.
5. Good English communication skill, both oral and written.
PE (Location: SH)
1. Product Engineer for QRC
Position Description:
1.Focus on QRC advanced solutions.
2.Responsible for integrating Cadence QRC into Cadence reference flows, for high-speed and advanced node designs (20nm/16nm).
3.Work on parasitic RC correlation and timing correlation between digital implementation tool and signoff tool, for better QoR.
4.Work on PVS-QRC solutions in both digital and analog design flows.
5.Provide in-depth technical consultant to foundry customers about Cadence digital signoff solutions, and usage of Cadence QRC in digital implementation and signoff cycles.
Position Requirements:
1.Knowledge in parasitic RC extraction methodology, accuracy analysis and correlation, and so on.
2.Expertise in extraction tools among various scales of designs, especially at advanced nodes.
3.Hands-on experiences in RTL-to-GDSII design projects, for designs from 500MHz to several GHz big chips.
4.Working experience in multi-nation IC design house is preferred.
5.Good communication in English and Chinese, team-spirit, self-motivated.
Intern (Location: SH)
時(shí)間安排： 4-5天/周，至少持續(xù)6-12個(gè)月
要求微電子/電子信息工程/軟件工程/計(jì)算機(jī)等相關(guān)專(zhuān)業(yè)的2015年及以后畢業(yè)的碩士、博士生。
1. RD Intern
Position Description:
This intern will work in Encounter placement team and 4 days/week or full time working for project development and analysis
Position Requirements:
1.EE/CS MS or PH.D, good at scripting: perl, tcl or C/C++ programming.
2.Could understand the concept of EDA backend design, especially placement and routing
3.Strong mathematics background is a plus.
4.Good communication in English and Chinese, good confidence and good self-motivation.
2. Intern - Product Engineer
Position Description:
1. Assist in digital reference flow development and optimization at advance nodes.
2. Be responsible for developing Perl/Tcl scripts for flow data post-processing, output analysis, etc.
3. Be responsible for various scripting and system development techniques for high productivity and efficiency.
Position Requirements:
1. MS or excellent undergraduate, EE or CS background.
2. Strong Tcl/Perl programming experience.
3. IC design knowledge and statistic timing analysis knowledge is a plus.
4. Unix System knowledge, vi/TK/CSH will be a strong plus.
5. Good communication in English and Chinese, good self-motivation and strong willing to learn new technologies
3. Intern - PVS/Assura rule deck development
Position Description:
Work in Cadence China Foundry Access Team, to assist in PVS/Assura rule deck development and qualification
1. Create test case with Virtuoso Layout for rule deck testing.
2. Develop various scripting for automatic test case generation flow and automatic QA flow.
3. Assist in rule deck development.
Position Requirements:
1. MS or excellent undergraduate, EE background. Semiconductor process knowledge is a must.
2. Layout experience with Virtuoso or other tools is a strong plus. Knowledge in DRC and LVS is preferred.
3. Linux System knowledge, vi/C shell/TCL/Perl will be a strong plus.
4. Good communication in English and Chinese, good self-motivation and strong willing to learn.
4. PV Intern
Position description:
1. Work with PV regression team for daily yellow and full QA review
2. Help PV team to deliver some system scripts (by perl/csh)
Position Requirements:
1. MS or excellent undergraduate, Strong perl programming experience
2. IC design knowledge is necessary, such as statistic timing analysis
3. Unix System knowledge, vi/TCL/TK/CSH will be plus
4. Good communication in English and Chinese, good confidence and good self-motivation
5. Can work 4 days/week and last for at least 6 months
三、簡(jiǎn)歷投遞方式
如有興趣請(qǐng)投遞簡(jiǎn)歷至job_china@cadence.com，并標(biāo)注你所申請(qǐng)的職位名稱(chēng)，請(qǐng)注意簡(jiǎn)歷的標(biāo)題：姓名-學(xué)校-專(zhuān)業(yè)-學(xué)歷-職位名稱(chēng)
對(duì)職位有任何疑問(wèn)，也可發(fā)郵件至該信箱，我們HR同事會(huì)及時(shí)給你回復(fù)并盡快安排面試。
Cadence(Nasdaq: CDNS)是全球電子設(shè)計(jì)自動(dòng)化(EDA)企業(yè)，從事軟件與硬件設(shè)計(jì)工具、芯片知識(shí)產(chǎn)權(quán)與設(shè)計(jì)服務(wù)。Cadence公司成立于1988年，總部位于加州圣荷塞，其設(shè)計(jì)中心、研發(fā)中心和銷(xiāo)售部門(mén)分布于世界各地。公司網(wǎng)站www.cadence.com.cn
1992年Cadence 公司進(jìn)入中國(guó)大陸市場(chǎng)，迄今已擁有大量的集成電路 (IC) 及系統(tǒng)設(shè)計(jì)客戶(hù)群體。在過(guò)去的二十年里，Cadence公司在中國(guó)不斷發(fā)展壯大，建立了北京、上海、深圳分公司以及北京研發(fā)中心、上海研發(fā)中心，并于2008年將亞太總部設(shè)立在上海，Cadence中國(guó)現(xiàn)有員工600余人。
北京研發(fā)中心(現(xiàn)位于北京市東城區(qū)北三環(huán)東路36號(hào)，北京環(huán)球貿(mào)易中心)和上海研發(fā)中心(現(xiàn)位于上海市浦東嘉里中心)主要承擔(dān)美國(guó)總部EDA軟件研發(fā)任務(wù)，力爭(zhēng)提供給用戶(hù)更加完美的設(shè)計(jì)工具和全流程服務(wù)。Cadence在中國(guó)擁有強(qiáng)大的技術(shù)支持團(tuán)隊(duì)，提供從系統(tǒng)軟硬件仿真驗(yàn)證、數(shù)字前端和后端及低功耗設(shè)計(jì)、數(shù)?；旌蟁F前端仿真與DFM以及后端物理驗(yàn)證、SiP封裝以及PCB設(shè)計(jì)等技術(shù)支持。我們的銷(xiāo)售方案中還包括提供數(shù)字及模擬IP、專(zhuān)業(yè)設(shè)計(jì)服務(wù)，VCAD團(tuán)隊(duì)為用戶(hù)提供高質(zhì)量、有效的設(shè)計(jì)和外包服務(wù)。
欲了解職位詳情請(qǐng)查詢(xún)“就業(yè)機(jī)會(huì)”或關(guān)注Cadence公眾微信平臺(tái)：Cadence中國(guó)招聘
二、招聘崗位
計(jì)算機(jī)，軟件工程，微電子，電子信息工程及相關(guān)專(zhuān)業(yè)
空缺職位
若干。軟件研發(fā)工程師、產(chǎn)品工程師和實(shí)習(xí)生職位空缺在北京和上海。
R&D
1. Senior/Software Engineer--Simulator front-end (Location: BJ)
Position Description:
1.Research and design simulator front end
Position Requirements:
1.Strong C++ programming and familiarity with development under Linux/Unix environment.
2.Proficiency with linux/unix tools.
3.Skills in one or more of script such as Python, Perl.
4.Familiar with build and version-control systems.
5.Good English communication skill both verbally and writing.
6.Good problem solving skill and team work spirit.
2. Senior Software Engineer--Virtuoso Design Environment (Location: BJ)
Position Description:
Custom digital and analog circuit designers must generate and interpret large amounts of complex simulation data. Virtuoso ADE accelerates design by enabling setup reuse, parallelizing and distributing compute-intensive simulation, and through extensive post-processing and visualization capabilities.
As an ADE programmer, you will:
1.Work closely with simulation and visualization teams in order to streamline tool flow and deliver new capabilities.
2.Implement internal algorithms, provide APIs for other tools to integrate, and provide GUI support for the end user.
3.Carefully consider data structures to handle large data sets.
4.Demonstrate strong OO knowledge using C++.
5.Write tests to validate your implementation.
Position Requirements:
1.Skilled in C++ programming, familiar with development under Linux/Unix environment;
2.Familiarity with GUI development, especially using the Qt toolkit is a plus
3.Familiarity with XML and/or SQL is a plus
4.Be familiar with Analog-signal design is a plus;
5.Good English communication skill both verbally and writing;
6.Good problem solving skill and team work spirit;
3. Senior/Software Engineer--Characterization (Location: BJ)
Position Description:
1.The positions are for a developer who will be responsible for designing, implementing, and maintaining library characterization and validation software for use with standard cells, memory and macro blocks, and IO cells
Position Requirements:
1.The candidates should have two or more years of experiences in developing EDA software.
2.Must be proficient in C, C++, TCL, and development in Linux/Unix.
3.Knowledge on semiconductor device is strong plus.
4.Experience with SPICE or SPICE-like circuit simulation is important.
5.Knowledge of Verilog and VHDL is also highly desirable.
6.Have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows.
7.Minimum Education Required / Minimum Experience Required : MS, EE, CS, Math or Physics 2
8.Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math or Physics 3-5
4. Senior Software Engineer--RF Simulator (Location: BJ)
Position Description:
1.The position is responsible for designing, implementing and maintaining Cadence Virtuoso platform for RF simulator. The engineer will be responsible for leading multiple development efforts through the development process, and working with a cross-functional team to ensure the software is tested, integrated and documented.
Position Requirements:
1. Skilled in C++ programming, familiar with development under Linux/Unix environment;
2.Exposure to the Cadence Virtuoso environment
3.Familiarity with Analog, RF or microwave design is a strong plus;
4.Good English communication skill both verbally and writing;
5.Good problem solving skill and team work spirit;
6. Education Requirement: Master in EE, CS, or related.
7.Experience with RF simulation methods, such as Harmonic Balance, Envelope and Shooting Newton
8.Understanding of distributed network theory
9.Background or coursework in RF/microwave circuits
5. Senior/Software Engineer--Power Route (Location: SH)
Position Description:
1. This position is for a R&D engineer to assist in development of special routing(power planning / power routing ...) solution of digital IC design in Encounter.
2. The candidate will be responsible for designing, developing, troubleshooting and debugging software programs of routing flow and related algorithms.
Position Requirements
1. The candidates should have strong software programming skill with C/C++ on Linux/Unix platform.
2. Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills
3. EDA software development experience or IC design knowledge, especially in backend
4. Know basic routing algorithms.
5. Good English communication skill, both oral and written.
PE (Location: SH)
1. Product Engineer for QRC
Position Description:
1.Focus on QRC advanced solutions.
2.Responsible for integrating Cadence QRC into Cadence reference flows, for high-speed and advanced node designs (20nm/16nm).
3.Work on parasitic RC correlation and timing correlation between digital implementation tool and signoff tool, for better QoR.
4.Work on PVS-QRC solutions in both digital and analog design flows.
5.Provide in-depth technical consultant to foundry customers about Cadence digital signoff solutions, and usage of Cadence QRC in digital implementation and signoff cycles.
Position Requirements:
1.Knowledge in parasitic RC extraction methodology, accuracy analysis and correlation, and so on.
2.Expertise in extraction tools among various scales of designs, especially at advanced nodes.
3.Hands-on experiences in RTL-to-GDSII design projects, for designs from 500MHz to several GHz big chips.
4.Working experience in multi-nation IC design house is preferred.
5.Good communication in English and Chinese, team-spirit, self-motivated.
Intern (Location: SH)
時(shí)間安排： 4-5天/周，至少持續(xù)6-12個(gè)月
要求微電子/電子信息工程/軟件工程/計(jì)算機(jī)等相關(guān)專(zhuān)業(yè)的2015年及以后畢業(yè)的碩士、博士生。
1. RD Intern
Position Description:
This intern will work in Encounter placement team and 4 days/week or full time working for project development and analysis
Position Requirements:
1.EE/CS MS or PH.D, good at scripting: perl, tcl or C/C++ programming.
2.Could understand the concept of EDA backend design, especially placement and routing
3.Strong mathematics background is a plus.
4.Good communication in English and Chinese, good confidence and good self-motivation.
2. Intern - Product Engineer
Position Description:
1. Assist in digital reference flow development and optimization at advance nodes.
2. Be responsible for developing Perl/Tcl scripts for flow data post-processing, output analysis, etc.
3. Be responsible for various scripting and system development techniques for high productivity and efficiency.
Position Requirements:
1. MS or excellent undergraduate, EE or CS background.
2. Strong Tcl/Perl programming experience.
3. IC design knowledge and statistic timing analysis knowledge is a plus.
4. Unix System knowledge, vi/TK/CSH will be a strong plus.
5. Good communication in English and Chinese, good self-motivation and strong willing to learn new technologies
3. Intern - PVS/Assura rule deck development
Position Description:
Work in Cadence China Foundry Access Team, to assist in PVS/Assura rule deck development and qualification
1. Create test case with Virtuoso Layout for rule deck testing.
2. Develop various scripting for automatic test case generation flow and automatic QA flow.
3. Assist in rule deck development.
Position Requirements:
1. MS or excellent undergraduate, EE background. Semiconductor process knowledge is a must.
2. Layout experience with Virtuoso or other tools is a strong plus. Knowledge in DRC and LVS is preferred.
3. Linux System knowledge, vi/C shell/TCL/Perl will be a strong plus.
4. Good communication in English and Chinese, good self-motivation and strong willing to learn.
4. PV Intern
Position description:
1. Work with PV regression team for daily yellow and full QA review
2. Help PV team to deliver some system scripts (by perl/csh)
Position Requirements:
1. MS or excellent undergraduate, Strong perl programming experience
2. IC design knowledge is necessary, such as statistic timing analysis
3. Unix System knowledge, vi/TCL/TK/CSH will be plus
4. Good communication in English and Chinese, good confidence and good self-motivation
5. Can work 4 days/week and last for at least 6 months
三、簡(jiǎn)歷投遞方式
如有興趣請(qǐng)投遞簡(jiǎn)歷至job_china@cadence.com，并標(biāo)注你所申請(qǐng)的職位名稱(chēng)，請(qǐng)注意簡(jiǎn)歷的標(biāo)題：姓名-學(xué)校-專(zhuān)業(yè)-學(xué)歷-職位名稱(chēng)
對(duì)職位有任何疑問(wèn)，也可發(fā)郵件至該信箱，我們HR同事會(huì)及時(shí)給你回復(fù)并盡快安排面試。