Cadence www.cadence.com 是全球的EDA (Electronic Design Automation) 軟件開(kāi)
    發(fā)商以及電子設(shè)計(jì)自動(dòng)化解決方案提供商.我們的產(chǎn)品涵蓋了電子設(shè)計(jì)的整個(gè)流程，包括
    系統(tǒng)級(jí)設(shè)計(jì)，功能驗(yàn)證，IC綜合及布局布線，模擬、混合信號(hào)及射頻IC設(shè)計(jì)，全定制集成
    電路設(shè)計(jì)，IC物理驗(yàn)證，PCB設(shè)計(jì)和硬件仿真建模等。全球知名半導(dǎo)體與電子系統(tǒng)公司均
    將Cadence軟件作為其全球設(shè)計(jì)的標(biāo)準(zhǔn)。
    Cadence在中國(guó)有2個(gè)研發(fā)中心，上海研發(fā)中心成立于2005年12月, 是Cadence全球成
    長(zhǎng)性的研發(fā)中心，承擔(dān)數(shù)字芯片設(shè)計(jì)，系統(tǒng)設(shè)計(jì)等各方面先進(jìn)電子設(shè)計(jì)自動(dòng)化工具的研發(fā)
    任務(wù)。目前我們的上海研發(fā)中心位于張江高科技園區(qū)碧波路690號(hào)張江微電子港8號(hào)樓，有
    研發(fā)人員近200人。
    Cadence北京研發(fā)中心 成立于2003年, 現(xiàn)位于海淀區(qū)海淀東三街2號(hào)歐美匯大廈，主要協(xié)
    同美國(guó)總部共同研發(fā)Virtuoso全定制設(shè)計(jì)平臺(tái)及其多模式仿真 (multi-mode simulation
    ) 產(chǎn)品。 Virtuoso全定制設(shè)計(jì)平臺(tái)是用于快速、硅精度設(shè)計(jì)的綜合系統(tǒng)。Virtuoso平臺(tái)
    包括：業(yè)界的規(guī)格驅(qū)動(dòng)的環(huán)境；使用通用語(yǔ)法、模型和方程式的多模式仿真；快速版
    圖設(shè)計(jì)，用于0.18微米以下工藝的先進(jìn)硅分析和全芯片混合信號(hào)集成仿真環(huán)境。使用該平
    臺(tái)，設(shè)計(jì)團(tuán)隊(duì)可以用從1微米到45納米的工藝迅速、準(zhǔn)確、按時(shí)地設(shè)計(jì)出硅片.
    我們正在上海和北京尋找軟件研發(fā)工程師和產(chǎn)品測(cè)試工程師，同時(shí) 有多個(gè)實(shí)習(xí)生職位空
    缺，歡迎微電子，電子，計(jì)算機(jī)，軟件工程，物理，數(shù)學(xué)及相關(guān)專業(yè)應(yīng)屆畢業(yè)碩士/博士
    加入我們！
    如有興趣請(qǐng)投遞簡(jiǎn)歷至 job_china@cadence.com，并標(biāo)注你申請(qǐng)的職位名稱。
    對(duì)職位有任何疑問(wèn)，也可發(fā)郵件至該信箱，我們HR同事會(huì)及時(shí)給你回復(fù)并盡快安排面試。
    1. PV(產(chǎn)品驗(yàn)證/測(cè)試) Intern for Regression(回歸) system development(Location:
    SH)
    每周保證4天，維持半年以上，計(jì)算機(jī)科學(xué)與技術(shù)，軟件工程等相關(guān)專業(yè)的2012(表現(xiàn)好可
    以轉(zhuǎn)正),2013年畢業(yè)的研究生
    Position Description
    1.Need 4 days/week or full time over 6 months working with PV regression team
    for daily yellow and full QA review
    2.Help PV team deliver some system scripts (by perl/csh)
    Requirement:
    1.MS or excellent undergraduate, good at programming, especially for perl, cs
    h.
    2.Should understand data base & the concept about regression testing.
    3.Good communication in English and Chinese, good confidence and good self-mo
    tivation.
    If you have interest, PLS send your CV to job_china@cadence.com
    2. PV(產(chǎn)品驗(yàn)證/測(cè)試) Intern for STA(靜態(tài)時(shí)序分析) (Location: SH)
    每周保證4天，維持半年以上，是微電子、集成電路等相關(guān)專業(yè)的2013年畢業(yè)的研究
    生
    Position description:
    1.This intern will work in Encounter Common Timing Engine Product Validation
    team. The responsibilities include:
    a) Assist in Cadence STA product and engines development and validation
    b) validate comprehensive STA test cases for Encounter Digital Implementation
    System and Encoutner Timing System
    c) Develop and maintain system and infrastructure for high productivity and e
    fficiency with various scripting and system development techniques
    Requirement:
    1.MS or excellent undergraduate, Strong perl programming experience.
    2.IC design knowledge is necessary, statistic timing analysis knowledge is a
    strong plus
    3.Unix System knowledge, vi/TCL/TK/CSH will be plus
    4.Good communication in English and Chinese, good confidence and good self-mo
    tivation.
    5.Commitment to work as intern at least 4 days per week for more than 6 month
    s
    If you have interest, PLS send your CV to job_china@cadence.com
    3. Intern for Foundry support (Location: SH)
    每周保證4天，維持半年以上，是電子信息工程、材料物理(半導(dǎo)體方向)等相關(guān)專業(yè)
    的2013年畢業(yè)的研究生
    Position description:
    Work in Cadence Foundry Access Team in Shanghai. Major responsibilities inclu
    de:
    1.Develop and maintain library QA flows for our foundry partners in Shanghai;
    2.Support customers in Cadence library database generation;
    3.Assist in digital reference flow development
    Requirement:
    1.MS or excellent undergraduate majored in CS/EE or related area;
    2.Strong desires to learn and explore new technologies, good analysis and pro
    blem solving skills;
    3.Be familiar with Cshell and Perl/Tcl programming;
    4.Know basics of digital IC design and implementation and basics of digital d
    esign kit.
    5.Understanding of basic design rules below 65nm process nodes is strongly pr
    eferred;
    6.Good communication in oral and written English
    If you have interest, PLS send your CV to job_china@cadence.com
    4. PV Intern for NanoRoute(Location: SH)
    每周保證4天，維持半年以上，是微電子、集成電路等相關(guān)專業(yè)的2013年畢業(yè)的研究
    生
    Position description:
    This intern will work in P&R Product Validation team. The responsibilities in
    clude:
    1.Assist in Cadence NanoRoute product and engines development and validation
    ;
    2.Validate comprehensive NanoRoute test cases for Encounter Digital Implement
    ation System ;
    3.Develop and maintain system and infrastructure for high productivity and ef
    ficiency with various scripting and system development techniques;
    Requirement:
    1.MS or excellent undergraduate
    2.Digital IC design knowledge is necessary
    3.Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
    4.Good communication in English and Chinese, good confidence and self-motivat
    ion.
    5.Commitment to work as intern for at least 6 months
    If you have interest, PLS send your CV to job_china@cadence.com
    5.PV Intern for GPS (Global Physical Synthesis) (Location: SH)
    每周保證4天，維持半年以上，是微電子、集成電路等相關(guān)專業(yè)的2013年畢業(yè)的研究
    生
    Position description:
    This intern will work in ICD (P&R) Product Validation team. The responsibilit
    ies include:
    1.Assist in Cadence GPS product and engines development and validation
    2.Validate comprehensive GPS test cases for Encounter Digital Implementation
    System
    3.Develop and maintain system and infrastructure for high productivity and ef
    ficiency with various scripting and system development techniques
    Requirement:
    1.MS or excellent undergraduate, Strong perl programming experience.
    2.IC design knowledge is necessary, statistic timing analysis knowledge is a
    strong plus
    3.Unix System knowledge, vi/TCL/TK/CSH will be plus.
    Good communication in English and Chinese, good confidence and good self-moti
    vation.
    If you have interest, PLS send your CV to job_china@cadence.com
    6. PV (產(chǎn)品驗(yàn)證) Intern for Circuit Simulation (Location: BJ)
    Position Description:
    1.Work together with a group of professionals on a variety of PV/QA projects
    to enhance circuit simulation product quality.
    Requirements:
    1.Students who are pursuing masters degree in Microelectronics or EE.
    2.Customer IC design experience.
    3.UNIX/Linux experience.
    If you have interest, PLS send your CV to job_china@cadence.com
    Cadence Beijing R&D
    1. Senior Developer (Location: BJ)
    Position Description:
    1.The positions are for a developer who will be responsible for designing, im
    plementing, and maintaining library characterization and validation software
    for use with standard cells, memory and macro blocks, and IO cells.
    Requirements:
    1.The candidates should have experiences in developing EDA software.
    2.Must be proficient in C, C , TCL, and development in Linux/Unix.
    3.Knowledge on semiconductor device is strong plus.
    4.Experience with SPICE or SPICE-like circuit simulation is important.
    5.Knowledge of Verilog and VHDL is also highly desirable.
    6.The ideal candidate would have a good understanding of library characteriza
    tion, IP design, static timing analysis, power analysis, and signal integrity
    analysis flows.
    7.Minimum Education Required / Minimum Experience Required : Master or Ph.D.
    in MS, EE, CS, Math or Physics
    If you have interest, PLS send your CV to job_china@cadence.com
    2. Product Verification Engineer (Location: BJ)
    Position Description:
    1.The positions are for a PV who will be responsible for designing, implement
    ing, and maintaining library characterization and validation software for use
    with standard cells, memory and macro blocks, and IO cells.
    Requirements:
    1.The candidates should have experiences in developing EDA software.
    2.Must be proficient in C, C , TCL, and development in Linux/Unix.
    3.Knowledge on semiconductor device is strong plus.
    4.Experience with SPICE or SPICE-like circuit simulation is important.
    5.Knowledge of Verilog and VHDL is also highly desirable.
    6.The ideal candidate would have a good understanding of library characteriza
    tion, IP design, static timing analysis, power analysis, and signal integrity
    analysis flows.
    7.Minimum Education Required / Minimum Experience Required : Master or Ph.D.
    in MS, EE, CS, Math or Physics
    If you have interest, PLS send your CV to job_china@cadence.com
    3. Senior Software Engineer for Fastspice Simulator (Location: BJ)
    Position Description
    1.Maintain and develop Cadence fastspice simulator.
    2.Be responsible for writing specifications, designing and implementing produ
    ct enhancements and fixes.
    3.Needs to work with other global R&D teams..
    Position Requirements
    1.Education requirement: Master or Ph.D. in EE/CS/related research area.
    2.Must be skilled in C/C programming, familiar with development under Linux
    /Unix environment.
    3.Strong background in numerical computation and programming.
    4.Knowledge of Analog Mixed-signal design and semiconductor device is a stron
    g plus.
    5.Good English communication skills both verbally and in writing.
    If you have interest, PLS send your CV to job_china@cadence.com
    4. Senior Software Engineer for RF simulator (Location: BJ)
    Position Description:
    1.Develop and maintain Cadence state-of-art RF simulation product
    2.Be able to work with a cross-functional team to ensure the software is test
    ed, integrated and documented.
    Position Requirements:
    1.Education Requirement: Master in EE, CS, or related.
    2.Be proficient in C/C Unix development
    3.Have a proven ability to learn from and work with an engineering and cross-
    functional team to deliver innovative products in a production environment.
    4.Good command in written and oral English.
    5.Experience in RF design is a plus.
    If you have interest, PLS send your CV to job_china@cadence.com
    5. Senior Software Engineer for Virtuoso ADE GXL (Location: BJ)
    Position Description:
    1.Dealing with manufacturing variation is becoming an increasingly important
    aspect of the custom digital and analog circuit design process. Virtuoso ADE
    GXL is a software tool for designers that offers statistical analysis, yield
    improvement, and design optimization capabilities to address this growing pro
    blem. We are seeing a talented software developer with a strong background in
    statistical analysis, data mining and modeling.
    Position Requirements:
    1.Strong background in statistical analysis, data mining, and modeling
    2.Demonstrated proficiency in C and general software development skills
    3.Master in Computer Science or Electrical Engineering required, PhD preferre
    d.
    4.Excellent communication skill in both mandarin and English.
    5.Working knowledge of Matlab a plus.
    6.Experience with Cadence Virtuoso or analog circuit design a plus.
    If you have interest, PLS send your CV to job_china@cadence.com
    6.Senior Software Engineer for Devices Compact Model (Location: BJ)
    Position Description:
    1.The position is for devices compact model engineer responsible for developi
    ng, implementing and maintaining device compact models in SPICE-like circuit
    simulation software. The engineer will be responsible for leading multiple de
    velopment efforts through the development process, including writing specific
    ations, designing and implementing product improvements and fixes. The engine
    er must have a proven ability to learn from work and work with a cross-functi
    onal team to deliver innovative products.
    Position Requirements
    1.Deep knowledge of Device Physics
    2.Skilled in C/C programming, familiar with development under Linux/Unix en
    vironment;
    3.Be familiar with numerical methods is a plus;
    4.Be familiar with Analog-signal design is a plus;
    5.Good English communication skill both verbally and writing;
    6.Good problem solving skill and team work spirit;
    7.Software Configuration Management (CM) Engineer (Location: BJ)
    Position Description:
    1.This position involves managing daily software build, test, and release pro
    cesses, and configuration management support for R&D/PV/PE. The responsibilit
    y also includes maintaining and enhancing the existing automation systems, de
    signing and developing new automation systems, software integration, and proj
    ect management.
    2.The candidate will also work closely with cross functional teams to diagnos
    e and resolve problems.
    Position Requirements:
    1.MS in Computer Science or BS in Computer Science with Software Configuratio
    n Management, IT, or Software Engineering experience.
    2.Familiar with Shell, Perl, and/or other programming languages.
    3.Familiar with GNU Make, GCC/G , and/or other compilers.
    4.Experience of Unix/Linux system.
    5.Good problem solving & analysis skills.
    6.Good interpersonal, verbal, and written communication skills.
    7.Fast and self learner.
    8.IT background is welcomed.
    If you have interest, PLS send your CV to job_china@cadence.com
    8.Senior Software Engineer for Verilog-A simulator development(Location: BJ)
    Position Description:
    1.Develop, enhance and maintain Verilog-A simulator.
    Requirements:
    1.Familiar with Spice, Verilog-A, Verilog-AMS language
    2.Skilled in C programming, familiar with development under Linux/Unix envi
    ronment.
    3.Analog circuit or digital simulator development experiences.
    4.Well understanding on circuit simulation technology, including MNA, dc, tra
    n method.
    5.Good mathematic background & knowledge.
    6.Be familiar with Analog Mixed-signal design is a plus
    7.EE or CS Master degree of above
    If you have interest, PLS send your CV to job_china@cadence.com